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IBIS4-6600 CYII4SM6600AB
6.6 MP CMOS Image Sensor
Features

Description
The IBIS4-6600 is a solid-state CMOS image sensor that integrates complete analog image acquisition, and a digitizer and digital signal processing system on a single chip. This image sensor has a resolution of 6.6 MPixel with 2210 x 3002 active pixels. The image size is fully programmable for user-defined windows. The pixels are on a 3.5 m pitch. This sensor is available in a Monochrome version or Bayer (RGB) patterned color filter array. The user programmable row and column start and stop positions enable windowing down to 2x1 pixel window for digital zoom. Sub sampling reduces resolution while maintaining the constant field of view. The analog video output of the pixel array is processed by an on-chip analog signal pipeline. Double Sampling (DS) eliminates the fixed pattern noise. The programmable gain and offset amplifier maps the signal swing to the ADC input range. A 10-bit ADC converts the analog data to a 10-bit digital word stream. The sensor uses a three-wire Serial-Parallel (SPI) interface. It operates with a single 2.5V power supply and requires only one master clock for operation up to 40 MHz. It is housed in a 68-pin ceramic LCC package. This data sheet enables you to develop a camera system, based on the described timing and interfacing given in the following sections. Figure 1. IBIS4-6600 Image Sensor
2210 (H) x 3002 (V) Active Pixels 3.5 m X 3.5 m Square Pixels 1 inch Optical Format Monochrome or Color Digital Output Frame Rate: 5 fps (2210 x 3002) 89 fps (640 x 480) High Dynamic Range Modes: Double Slope, Non Destructive Read out (NDR) Electronic Rolling Shutter Master Clock: 40 MPS/40 MHz Limited Supplies: 2.5V and 3.3V -30C to +65C Operational Temperature Range 68-Pin LCC Package Power Dissipation: 0.19W

Applications

Machine vision Biometry Document Scanning
Cypress Semiconductor Corporation Document Number: 001-02366 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 17, 2009
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Specifications
General Specifications
Parameter Pixel Architecture Pixel Size Resolution Pixel Rate Shutter Type Full Frame Rate 3T-Pixel 3.5 m x 3.5 m 2210 x 3002 40 MHz Electronic Rolling Shutter 5 frames/second Increases with ROI read out and/or subsampling The resolution and pixel size results in a 7.74 mm x 10.51 mm optical active area. Using a 40 MHz system clock and 1 or 2 parallel outputs Specification Remarks
Electro Optical Specifications
Parameter FPN (local) PRNU (local) Conversion Gain Output Signal Amplitude Saturation Charge Sensitivity (peak) Sensitivity (visible) Peak QE * FF Peak Spectral Response Fill Factor Dark Current Dark Signal Non Uniformity Temporal Noise S/N Ratio Spectral Sensitivity Range Optical Cross Talk Power Dissipation <0.20% <1.5% Conversion Gain 0.6V 21.500 e411 V.m2/W.s 4.83 V/lux.s 328 V.m2/W.s 2.01 V/lux.s 25% 0.13 A/W 35% 3.37 mV/s 78 e-/s 8.28 mV/s 191 e-/s 24 RMS e895:1 (59 dB) 400 - 1000 nm 15% 4% 190 mW To the first neighboring pixel To the second neighboring pixel Typical (including ADCs) At 650 nm (85 lux = 1 W/m2) 400-700 nm (163 lux = 1 W/m2) Average QE*FF = 22% (visible range) Average SR*FF = 0.1 A/W (visible range) See the section Spectral Response Curve on page 3. Light sensitive part of pixel (measured) Typical value of average dark current of the whole pixel array (at 21C) Dark current RMS value (at 21C) Measured at digital output (in the dark) Measured at digital output (in the dark) Specification RMS of signal level At output (measured) At nominal conditions Remarks RMS% of saturation signal
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Spectral Response Curve
Figure 2. Spectral Response Curve
0.14 QE 30% QE 20%
0.12
0.1
Spectral response [A/W]
0.08
QE 10%
0.06
0.04
0.02
0 400
500
600
700 Wavelenght [nm]
800
900
1000
Figure 2 shows the characteristics of the spectral response. The curve is measured directly on the pixels. It includes the effects of nonsensitive areas in the pixel, for example, interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE * FF is 25% approximately 650 nm. In view of a fill factor of 35%, the QE is close to 70% between 500 and 700 nm.
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Electro Voltaic Response Curve
Figure 3. Electro Voltaic Response Curve
0.7
0.6
0.5
Output swing [V]
0.4
0.3
0.2
0.1
0 0 5000 10000 # electrons 15000 20000 25000
Figure 3 shows the pixel response curve in linear response mode. This curve is the relation between the electrons detected in the pixel and the output signal. The resulting voltage-electron curve is independent of any parameters, for example, integration time. The voltage to electrons conversion gain is 43 V/electron. Table 1. Features and General Specifications Feature Electronic shutter type Integration time control Windowing (ROI) Sub Sampling Modes Extended Dynamic Range Analog Output Digital Output Supply Voltage VDD Logic Levels Interface Package Rolling shutter 60 s - 1/frame period Randomly programmable ROI read out Several sub sample modes can be programmed (refer Table 7 on page 12) Dual slope (up to 90 dB optical dynamic range) and nondestructive read out mode The output rate of 40 Mpixels/s can be achieved with two analog outputs, each working at 20 Mpixel/s Two on-chip 10-bit ADCs at 20 Msamples/s are multiplexed to one digital 10-bit output at 40 Msamples/s Nominal 2.5V (some supplies require 3.3V for extended dynamic range) 2.5V Serial-to Parallel Interface (SPI) 68-pins LCC Specification/Description
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Electrical Specifications
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Stresses beyond those listed under Table 2 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these or any other conditions beyond those indicated in the operational sections are not implied. Table 2. Absolute Maximum Ratings Symbol VDD VIN VOUT IIO TL TST H ESD
[1]
Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Current Drain Per Pin; Any Single Input or Output Lead Temperature (5 seconds soldering) Storage Temperature Humidity (Relative) ESD Susceptibility
Value -0.5 to 3.3 -0.5 to (VDD + 0.5) -0.5 to (VDD + 0.5) 50 350 -30 to +85 85% at 85 C 2000
Unit V V V mA C C V
Recommended Operating Conditions
Symbol VDD TA DC Supply Voltage Commercial Operating Temperature Parameter Min 2.5 -30 Typ 2.5 24 Max 3.3 +65 Unit V C
All parameters are characterized for DC conditions after thermal equilibrium is established. Unused inputs must always be tied to an appropriate logic level, for example, VDD or GND. This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields. However, you must take normal precautions to avoid applying voltages higher than the maximum rated voltages to this high impedance circuit.
DC Electrical Conditions
Symbol VIH VIL IIN VOH VOL IDD Characteristic Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Operating Current VIN = VDD or GND VDD=min; IOH= -100 mA VDD=min; IOH= 100 mA System clock <= 40 MHz 70 Condition Min VDD-0.5 -0.6 -10 VDD-0.5 0.5 80 0.6 +10 Max Unit V V A V V mA
Note 1. VDD = VDDD = VDDA (VDDD is supply to digital circuit, VDDA to analog circuit).
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Sensor Architecture and Operation
Floor Plan
Figure 4. Floor Plan
S E NS OR
eos _yl
IMAG E C OR E
addres s able y-s hift regis ter + s ub-s ampling
addres s able y-s hift regis ter + s ub-s ampling
eos _yr
s elect tri r
res et tri l
ADC , 10 bit
pixel array
res et and s elect drivers
2210 x 3002 (excl. dark + dummy pixels )
res et and s elect drivers
P ixel (0,0)
clk_y s ync_yr
clk_y s ync_yl
column amplifiers clk_x s ync_x
addres s able x-s hift regis ter + s ub-s ampling
addres s & data bus
Dig. logic
SPI
DAC DAC in analog output (2)
Dig. logic
Figure 4 shows the architecture of the designed image sensor. It consists of the pixel array, shift registers for the readout in x and y direction, parallel analog output amplifiers, and column amplifiers that correct for the fixed pattern noise caused by threshold voltage nonuniformities. Reading out the pixel array starts by applying a y clock pulse to select a new row, followed by a calibration sequence to calibrate the column amplifiers (row blanking time). Depending on external bias resistors and timing, typically this sequence takes about seven seconds every line (baseline). This sequence is necessary to remove the Fixed Pattern Noise of the pixel and of the column amplifiers themselves (by a Double Sampling technique). Pixels can also be read out in a nondestructive manner. Two DACs are added to make the offset level of the pixel values adjustable and equal for the two output buses. A third DAC is used to connect the buses to a stable voltage during the row blanking period, or reset the buses continuously in case of a nondestructive readout. Document Number: 001-02366 Rev. *E
Two 10-bit ADCs running at 20 Msamples/s convert the analog pixel values. The digital outputs are multiplexed to one digital 10-bit output at 40 Msamples/s. Note that these blocks are electrically completely isolated from the sensor part, except for the multiplexer, for which the settings are uploaded through the shared address and data bus. The x and y shift registers have a programmable starting point. The possibilities of the starting point are limited because of limitations imposed by subsampling requirements. The start address is uploaded through the serial to parallel interface. Most of the signals for the image core shown in Figure 4 are generated on-chip by the sequencer. This sequencer also allows running the sensor in basic modes, not fully autonomous.
s equencer
ADC , 10 bit
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Pixel
Architecture The pixel architecture is the classic three-transistor pixel, as shown in Figure 5 The pixel is implemented using the high fill factor technique patented by FillFactory (US patent No. 6,225,670 and others). Figure 5. 3T Pixel Architecture Color Filter Array The IBIS4-6600 can also be processed with a Bayer RGB color pattern. Pixel (0,0) has a green filter and is situated on a green-red row. Green1 and Green2 are separately processed color filters and have a different spectral response. Green1 pixels are located on a blue-green row, and green2 pixels are located on a green-red row. Figure 6. RGB Bayer Alignment
Vdd
reset
M1 M2
select
selec
M3
output (column)
FPN and PRNU Fixed Pattern Noise correction is done on-chip. Raw images taken by the sensor typically feature a residual (local) FPN of 0.35% RMS of the saturation voltage. The Photo Response Non Uniformity (PRNU), caused by the mismatch of photodiode node capacitances, is not corrected on chip. Measurements indicate that the typical PRNU is about 1.5% RMS of the signal level.
Figure 7 shows the response of the color filter array as function of the wavelength.
Figure 7. Typical Response Curve of the RGB Filters
0.140
0.120
0.100
spectral response [A/W]
0.080
blue green 1 green 2 red
0.060
mono
0.040
0.020
0.000 400 500 600 700 wavelength [nm] 800 900 1000
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Figure 8. Relative Response Graph
1
0.9
0.8
0.7
0.6
relative response
blue
0.5
green 1 green 2 red
0.4
0.3
0.2
0.1
0 400 500 600 700 wavelength (nm) 800 900 1000
Dark and Dummy Pixels Figure 9 shows a plan of the pixel array. The sensor is designed in portrait orientation. A ring of dummy pixels surrounds the active pixels. Black pixels are implemented as "optical" black pixels. Figure 9. Floor Plan Pixel Array
Dummy ring of pixels , s urrounding complete pixel array. not read
R ing of dummy pixels , covered with black layer, readable R ing of 2 dummy pixels , illuminated, readable
3002
array of active pixels , read 3002x 2210
3014
2222
2210
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Pixel Rate The pixel rate for this sensor is high enough to support a frame rate greater than 75 Hz for a window size of 640 x 480 pixels (VGA format), and 23 pixels over scan in both directions. Taking into account a row blanking time of 7.2 s (as baseline, refer the following calculations), this requires a minimum pixel rate of approximately 40 MHz. The final bandwidth of the column amplifiers, output stage, and more is determined by external bias resistors. Taking into account a pixel rate of 40 MHz, a full frame rate of a little more than 5 frames/s is obtained. The frame period of the IBIS4-6600 sensor is calculated as: => Frame period = (Nr. Lines * (RBT + pixel period * Nr. Pixels)) In this equation: Nr. Lines: Number of Lines read out each frame (Y) Nr. Pixels: Number of pixels read out each line (X) RBT: Row Blanking Time = 7.2 s (typical) Table 3. Frame Rate vs. Resolution Image Resolution (Y*X) 3002 x 2210 1501 x 1104 640 x 480 Frame Rate [frames/s] 5 14 89
Pixel period: 1/40 MHz = 25 ns Example: Read out time of the full resolution at nominal speed (40 MHz pixel rate): => Frame period = (3002 * (7.2 s + 25 ns * 2210)) = 187.5 ms => 5.33 fps.
Region of Interest (ROI) Read Out
Windowing is easily achieved by uploading the starting point of the x and y-shift registers in the sensor registers (refer Table 10 on page 17). This downloaded starting point initiates the shift register in the x and y-direction, triggered by the Y_START (initiates the Y-shift register) and the Y_CLK (initiates the X-shift register) pulse. The minimum step size for the x-address is 24 (only even start addresses can be chosen) and 1 for the Y-address (every line can be addressed). The frame rate increases in an almost linear manner when fewer pixels are read out. Table 3 lists the achievable frame rates with ROI read out.
Frame Readout Time [ms] 187.5 67 11 ROI read out 11
Comment Full resolution
Output Amplifier
The output amplifier subtracts the reset and signal voltages from each other to cancel FPN as much as possible (shown in Figure 10). The DAC that is used for offset adjustment consists of two DACs. One DAC is used for the main offset (DAC_raw). The other enables fine tuning to compensate the offset difference between the signal paths arriving at the two amplifiers A1 and A2 (DAC_fine). With the analog multiplexer, the signals S1 and S2 from the two buses can be combined to one pixel output at full pixel rate (40 MHz). However, the two analog signals S1 and S2 can also be available on two separate output pins to allow a higher pixel rate. The third DAC (DAC_dark) puts its value on the buses during the calibration of the output amplifier. In case of nondestructive readout (no double sampling), bus1_R and bus2_R are continuously connected to the output of the DAC_fine to provide a reference for the signals on bus1_S and bus2_S. The complete output amplifier can be put in standby by setting the corresponding bit in the AMPLIFIER register.
Figure 10. Output Amplifier Architecture
programmable gain amplifiers bus1 S bus1_R bus2 S bus2_R + A1 S1 analog multiplexer S2 1 Stage 1 DAC_raw / DAC_fine DAC_dark Stage 2 Pixel output 2 output drivers Pixel output 1
+ A2
Stage 3
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Stage 1: Offset, FPN Correction, and Multiplexing In the first stage, the signals from the buses are subtracted and the offset from the DACs is added. After a system reset, the analog multiplexer is configured for two outputs (see the bit settings in the AMPLIFIER Register on page 22). In case ONE_OUT is set to 1, the two signals S1 and S2 are multiplexed to one output (output 1). The amplifiers of Stage 2 and Stage 3 of the second output path are then put in standby. The speed and power consumption of the first stage can be controlled through the resistor connected to CMD_OUT_1. Stage 2: Programmable Gain Amplifier The second stage provides the gain, which is adjustable between 1.36 and 17.38 in steps of approximately 20.25 (~1.2). An overview of the gain settings is given in Table 4. The speed and power consumption of the second stage can be controlled through the resistor connected to CMD_OUT_2. Table 4. PGA Gain Settings Bits 0000 0001 0010 0011 0100 0101 0110 0111 DC Gain 1.36 1.64 1.95 2.35 2.82 3.32 3.93 4.63 Bits 1000 1001 1010 1011 1100 1101 1110 1111 DC Gain 5.40 6.35 7.44 8.79 10.31 12.36 14.67 17.38
Stage 3: Output Drivers The speed and power consumption of the third stage can be controlled through the resistor connected to CMD_OUT_3. The output drivers are designed to drive a 20 pF output load at 40 Msamples/s with a bias resistor of 100 k. Offset DACs Figure 11 shows how the DAC registers influence the black reference voltages of the two different channels. The offset is mainly given through DAC_raw. DAC_fine can be used to shift the reference voltage of bus 2 up or down to compensate for different offsets in the two channels.
Figure 11. Offset for the Two Channels through DAC_RAW and DAC_FINE
10K DAC_RAW_REG<0:7 DAC_raw out 200K blackref bus1
rcal
RCAL
+
pad
VCAL
RCAL_DAC_OUT
VDDA 50K
10K
blackref bus2
DAC_FINE_REG<0:7
DAC_fine out 50K rcal
200K
floating
GNDA
Note that in this figure, "K" represents K.
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Assume that Voutfull is the voltage that depends on the bit values that are applied to the DAC and ranges from:
Voutfull : 0 (bit values 00000000 )
VDDA (1
1 ) (bit values 11111111 ) 28
Externally, the output range of DAC_raw can be changed by connecting a resistor Rcal to RCAL_DAC_OUT and applying a voltage Vcal. The output voltage Vout of DAC_raw follows the relation (R = 10 k).
Vout
Special case:
R Rcal Voutfull 2 R Rcal
R 2R Rcal
Vcal
Rcal = then Vout = Voutfull (for example, for DAC_fine) Rcal = 0, Vcal = GND ............................. then Vout = Voutfull/2 A similar relation holds for the output range of DAC_DARK (RCAL_DAC_DARK can be used to tune the output range of this DAC).
Analog to Digital Converter
The IBIS4-6600 has a two 10-bit flash analog digital converters. The ADCs are electrically separated from the image sensor. The inputs of the ADC must be tied externally to the outputs of the output amplifiers. One ADC samples the even columns and the other samples the odd columns. Alternatively, one ADC can also sample all the pixels. Table 5. ADC Specifications Parameter Input Range Quantization Nominal Data Rate DNL(Linear Conversion Mode) INL (Linear Conversion Mode) Input Capacitance Conversion Law Setting the ADC Reference Voltages Figure 12. ADC Resistor Ladder
VDDA_ADC
Specification Set by External Resistors (Refer the section Setting the ADC Reference Voltages) 10 Bits 20 Msamples/s Typ. < 0.4 LSB RMS Typ. < 3.5 LSB < 2 pF Linear/Gamma corrected
VHIGH_ADC ~ 1.5V
RADC = 577 Ohm 150 Ohm (ESD)
Internal
The internal resistance has a value of approximately 577 . Only 277 of this internal resistance is actually used as reference for the internal ADC. This causes the actual ADC voltage range to become half of the voltage difference between VHIGH_ADC and VLOW_ADC. This results in the values listed Table 6 for the external resistors. Table 6. ADC Resistor Values Resistor RVHIGH_ADC RInternal RVLOWADC Value () 560 577 220
277 Ohm
High reference voltage used by ADC
Low reference voltage used by ADC 150 Ohm (ESD) VLOW_ADC ~ 0.42V
GND
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Sub Sample Modes
To increase the frame rate for lower resolution and regions of interest, several sub sampling modes are implemented. The possible sub sample modes are listed in Table 7. The bits can be programmed in the IMAGE_CORE register (refer Table 10 on page 17). To preserve the color information, two adjacent pixels are read in any mode. The number of pixels that is not read varies from mode to mode. This is designed as a repeated block 24 pixels wide, which is the lowest common multiple of the modes described. Including the dummy pixels and the two additional rows/columns, the number of starting coordinates for the x and y shift register is 99 in the X direction and 138 in the Y direction. The total number of pixels, excluding dummy pixels, is a multiple of 24, and two additional pixels to have the same window edges independently of the sub sampling mode.
In the X direction, two columns are always addressed at the same moment, because the signals from the odd and even columns must be put simultaneously on the corresponding bus. In the Y direction, the rows are addressed one by one. This results in slightly different implementations of the sub-sampling modes for the two directions (Refer Figure 13 and Figure 14 on page 13). Table 7. Subsample Patterns Mode A B C D E Bits 000 001 010 011 1xx Read 2 2 2 2 2 Step 2 4 6 8 12 Description Default mode (Skip 2) (Skip 4) (Skip 6) (Skip 10)
Figure 13. X-Sub Sampling
24 column amplifiers
bus1_S bus1_R bus2_S bus2_R
Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Logic selecting 2 collumns Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
scan direction
A B C D E
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Shift register
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Figure 14. Y-Sub Sampling
shift registers on pixel pitch scan direction
Logic selecting 1 row
E
D
C
B
A
Table 8. Frame Rate vs. Sub Sample Mode Mode A B C D 63.2 VGA (p) VGA (p) + 23 VGA (l) VGA(l) + 23 Ratio 1:1 1:4 1:9 1:16 1:36 Resolution (Y*X) 3002 x 2210 1502 x 1106 1002 x 738 752 x 554 502 x 370 640 x 480 663 x 503 480 x 640 503 x 663 Frame time [mS] 187.4 52.3 25.7 15.8 8.2 12.3 13.1 11.1 11.9 Frame time [mS] 5.3 19.1 38.9 63.2 121.2 81.5 76.4 89.9 83.7
Figure 15 on page 14 shows the pixels read out in each color sub sampling mode.
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Figure 15. Pixel Readout in Various Subsample Modes
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode A
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode B
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode C
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode D
Mode E
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Electronic Shutter
An electronic shutter similar to a rolling curtain is implemented on-chip. As shown in Figure 17, there are two Y shift registers. One shift register points to the row that is currently being read out. The other shift register points to the row that is currently being reset. Both pointers are shifted by the same Y-clock and move over the focal plane. The integration time is set by the delay between both pointers. Figure 16. Electronic Shutter
Readout pointer
Integration time
Reset pointer
In case of a mechanical shutter, the two shift registers can be combined to simultaneously apply the pulses from both sides of the pixel array. This is to halve the influence of the parasitic RC times of the reset and select lines in the pixel array. This can result in a reduction of the row blanking time. This is the case when FAST_RESET in the SEQUENCER register is set to 1, or in the nondestructive readout modes 1 and 2. Figure 17. Electronic Rolling Shutter Operation
Line number
Reset sequence
Time axis Frame time Integration time
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High Dynamic Range Modes
Double Slope Integration The IBIS4-6600 has a feature called double slope integration to increase the optical dynamic range of the sensor. The pixel response can be extended over a larger range of light intensities by using a "dual slope integration" (patents pending). This is obtained by adding charge packets from a long and a short integration time in the pixel during the same exposure time. Figure 18 shows the response curve of a pixel in dual slope integration mode. The curve also shows the response of the same pixel in linear integration mode at the same light levels, with a long and short integration time. Dual slope integration is obtained by feeding a lower supply voltage to VDD_RESET_DS (for example, apply 2.0V to 2.5V). Note that for normal (single slope) operation, VDD_RESET_DS
1.8 1.6 1.4 1.2 1 0.8 0.6
Dual slope operation
must have the same value as VDD_RESET. The difference between VDD_RESET_DS and VDD_RESET determines the range of the high sensitivity, and as a result the output signal level at which the transition between high and low sensitivity occurs. Put the amplifier gain to the lowest value where the analog output swing covers digital input swing of the ADC. Increasing the amplification too much may boost the high sensitivity part over the whole ADC range. The electronic shutter determines the ratio of integration times of the two slopes. The high sensitivity ramp corresponds to "no electronic shutter", thus maximal integration time (frame read out time). The low sensitivity ramp corresponds to the electronic shutter value that is obtained in normal operation.
Figure 18. Double Slope Response
Output signal [V]
0.4 0.2 0 0% 20% 40%
Long integration time Short integration time
Relative exposure (arbitrary scale) 60% 80% 100%
NonDestructive Read Out (NDR) The default mode of operation of the sensor is with FPN correction (double sampling). However, the sensor can also be read out in a nondestructive method. After a pixel is initially reset, it can be read multiple times, without being reset. The initial reset level and all intermediate signals can be recorded. High light levels saturate the pixels quickly, but a useful signal is obtained from the early samples. For low light levels, use the later or latest samples. Essentially an active pixel array is read multiple times, and reset only once. The external system intelligence interprets the data. Table 9 on page 17 summarizes the advantages and disadvantages of nondestructive readout. Figure 19. Principle of NonDestructive Readout
time
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Table 9. NDR: Advantages and Disadvantages Advantages Disadvantages Low Noise, because it is true CDS. In the order of 10 e- or below. System memory required to record the reset level and the intermediate samples. High Sensitivity, because the conversion capacitance is kept rather Requires multiples readings of each pixel, thus higher data low. throughput. High Dynamic Range, because the results include signals for short Requires system level digital calculations. and long integrations times.
Sequencer and Registers
Figure 4 on page 6 showed several control signals that are needed to operate the sensor in a particular sub sampling mode, with a certain integration time, output amplifier gain, and more. Most of these signals are generated on-chip by the sequencer that uses only a few control signals. These control signals must be generated by the external system:

The relative position of the pulses is determined by a number of data bits that are uploaded in internal registers through a Serial to Parallel interface (SPI). Internal Registers Table 10 lists the internal registers with a short description. The registers are discussed in more detail in the following sections.
SYS_CLOCK, which defines the pixel rate (nominal 40 MHz), Y_START pulse, which indicates the start of a new frame, Y_CLOCK, which selects a new row and starts the row blanking sequence, including the synchronization and loading of the X-register.
Table 10. List of Internal Registers Register 0 (0000) Bit 11:0 0 Name SEQUENCER register NDR Description Selection of mode, granularity of the X sequencer clock, calibration, Default value <11:0>:"000100000000" Mode of readout: NDR = 0: normal readout (double sampling) NDR = 1: non-destructive readout 4 different modes of nondestructive readout (no influence if NDR = 0) 0 = normal operation 1 = reset of pixels before readout 0 = electronic shutter operation 1 = addressing from both sides
1:2 3 4 5 6 7 8 9 10
NDR_mode RESET_BLACK FAST_RESET
FRAME_CAL_MODE 0 = fast 1 = slow LINE_CAL_MODE CONT_CHARGE 0 = fast 1 = slow 0 = normal mode 1 = continuous precharge
GRAN_X_SEQ_LSB Granularity of the X sequencer clock GRAN_X_SEQ_MSB BLACK 0 = normal mode 1 = disconnects column amplifiers from buses, output of amplifier equals dark reference level 0 = normal mode 1 = continuous reset of all pixels Number of pixels to count (X direction). Max. 2222/2 (2210 real + 12 dummy pixels). Default value <10:0>:"01000000000"
11 1 (0001) 10:0
RESET_ALL NROF_PIXELS
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Table 10. List of Internal Registers (continued) Register 2 (0010) Bit 11:0 Name NROF_LINES Description Number of lines to count (Y direction) Max. 3014 (3002 real + 12 dummy pixels) Default value <11:0>:"101111000110" Integration time Default value <11:0>:"000000000001" Delay of sequencer pulses Default value <7:0>:"00000011" Delay of PIX_VALID pulse Delay of EOL/EOF pulses X start position (0 to 98) Default value <6:0>:"0000000" Y start position (0 to 137) Default value <7:0>:"00000000" Default value <7:0>:"00000000" LSB: odd, MSB: even 0 = normal operation sub sampling mode in X-direction sub sampling mode in X-direction Default value <9:0>:"0000010000" Output amplifier gain setting 0 = gain setting by GAIN<3:0> 1 = unity gain setting 0 = two analog outputs 1 = multiplexing to one output (out_1) 0 = normal operation 1 = amplifier in standby mode Delay of pixel clock to output amplifier Amplifier DAC raw offset Default value <7:0>:"10000000" Amplifier DAC fine offset Default value <7:0>:"10000000" DAC dark reference on output bus Default value <7:0>:"10000000"
3 (0011) 4 (0100)
11:0 7:0 0:3 4:7
INT_TIME DELAY DELAY_PIX_VALID DELAY_EOL/EOF X_REG Y_REG IMAGE CORE register TEST_mode X_SUBSAMPLE Y_SUBSAMPLE AMPLIFIER register GAIN<3:0> UNITY ONE_OUT STANDBY DELAY_CLK_AMP DAC_RAW_REG DAC_FINE_REG DAC_DARK_REG
5 (0101) 6 (0110) 7 (0111)
6:0 7:0 7:0 1:0 4:2 7:5
8 (1000)
9:0 3:0 4 5 6 7:9
9 (1001)
7:0
10 (1010) 7:0 11 (1011) 7:0
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Table 10. List of Internal Registers (continued) Register 12 (1100) 0 1 2 3 4 5 6:8 9 10 13 (1101) 14 (1110) 15 (1111) Bit 10:0 Name ADC register STANDBY_1 STANDBY_2 ONE SWITCH EXT_CLK TRISTATE DELAY_CLK_ADC GAMMA BITINVERT Reserved Reserved Reserved Mode 1 In this mode, the sensor is readout in the same method as for the nondestructive readout. However, electronic shutter control is not possible in this case, that is, the minimal (integration) time between two readings is equal to the number of lines that has to be read out (frame read time). The row lines are clocked simultaneously (left and right clock pulses are equal). Mode 2 In this mode, it is possible to have a shorter integration time than the frame read time. Rows are alternatingly read out with the left and right pointer. These two pointers can point to two different rows (see INT_TIME register). The integration time between two readings of the same row is equal to the number of lines that is set in the INT_TIME register multiplied by 2 plus 1, and is the minimal one line read time. In setting 3, the row that is read out by the left pointer is reset and read out (first Y_CLOCK), and the row that is read out by the right pointer is read out without being reset (second Y_CLOCK). In setting 4, both rows are read out without being reset (on the first Y_CLOCK the row is read out by the left pointer; on the second Y_CLOCK the row is read out by the right pointer). For both modes, the signals are read out through the same path as with destructive readout (double sampling), but the buses that are carrying the reset signals in destructive readout, are set to the voltage given by DAC_DARK in nondestructive readout. 0 = multiplexing of two ADC outputs 1 = disable multiplexing if ONE = 0: delay of output with one (EXT_CLK = 0) or half (EXT_CLK = 1) clock cycle if ONE = 1: switch between two ADCs 0 = internal clock (same as clock to X shift register and output amplifier) 1 = external clock 0 = normal operation 1 = outputs in tristate mode Delay of clock to ADCs and digital multiplexer 0 = linear conversion 1 = 'gamma' law conversion 0 = no inversion of bits 1 = inversion of bits 0 = normal operation 1 = ADC in standby Description Default value <10:0>:"00000000000"
Register Descriptions
SEQUENCER Register a. NDR (Bit 0) In normal operation (NDR = 0), the sensor operates in double sampling mode. At the start of each row readout, the signals from the pixels are sampled, the row is reset, and the signals from the pixels are sampled again. The values are subtracted in the output amplifier. When NDR is set to 1, the sensor operates in nondestructive readout (NDR) mode (refer Table 11). b. NDR_mode (Bit 1 and 2) These bits only influence the operation of the sensor in case NDR (bit 0) is set to 1. There are two modes for nondestructive readout (mode 1 and 2). Each mode needs two different frame readouts (setting 1 and 2 for mode 1, setting 3 and 4 for mode 2). a reset/readout sequence (reset_seq) and then one or several pure readout sequences (called read_seq hereafter). Table 11 gives an overview of the different NDR modes. Table 11. Overview of NDR Modes. Setting 1 2 3 4 Bits 00 01 10 11 NDR mode 1 1 2 2 Sequence reset read reset read
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c.
Reset_black (Bit 3)
If RESET_BLACK is set to 1, each line is reset before it is read out (except for the row that is read out by the right pointer in NDR Mode 2). This may be useful to obtain black pixels. d. Fast_reset (Bit 4) The fast reset option (FAST_RESET = 1) might be useful in case a mechanical camera shutter is used. The fast reset is done on a row-by-row basis, not by a global reset. A global reset means charging all the pixels at the same time, which may result in a huge peak current. Therefore, the rows can be scanned rapidly while the left and right shift registers are both controlled identically, so that the reset lines over the pixel array are driven from both sides. This reduces the reset (row blanking) time (when FAST_RESET = 1 the smallest X-granularity can be used). After the row blanking time, the row is reset and Y_CLOCK can be asserted to reset the next row. After a certain integration time, the read out can be done in a similar method. The Y shift registers are again synchronized to the first row. Both shift registers are driven identically, and all rows and columns are scanned for (destructive) readout. FAST_RESET = 1 puts the sequencer in such mode that the left and right shift registers are both controlled identically. e. Output Amplifier Calibration (Bit 5 and 6) Bits FRAME_CAL_MODE and LINE_CAL_MODE define the calibration mode of the output amplifier. During every row-blanking period, a calibration is done of the output amplifier. There are two calibration modes. The FAST mode (= 0) can force a calibration in one cycle. However, it is not
accurate and suffers from kTC noise, while the SLOW mode (= 1) can only make incremental adjustments and is noise free. Approximately 200 or more "slow" calibrations have the same effect as one "fast" calibration. Different calibration modes can be set at the beginning of the frame (FRAME_CAL_MODE bit) and for every subsequent row that is read (LINE_CAL_MODE bit). f. Continuous Charge (Bit 7) For some applications, it might be necessary to use continuous charging of the pixel columns instead of a precharge on every row sample operation. Setting bit CONT_CHARGE to 1 activates this function. The resistor connected to pin CMD_COL is used to control the current level on every pixel column. g. Internal Clock Granularities The system clock is divided several times on-chip. The X-shift-register that controls the column/pixel readout, is clocked by half the system clock rate. Odd and even pixel columns are switched to two separate buses. In the output amplifier, the pixel signals on the two buses can be combined to one pixel stream at 40 MHz. The clock that drives the X-sequencer can be a multiple of 2, 4, 8, or 16 times the system clock. Table 12 lists the settings for the granularity of the X-sequencer clock and the corresponding row blanking time (for NDR = 0). A row blanking time of 7.18 s is the baseline for almost all applications.
Table 12. Granularity of X-Sequencer Clock and Corresponding Row Blanking Time (for NDR = 0). Gran_x_seq_msb/lsb 00 01 10 11 h. Black (Bit 10) X-Sequencer Clock 2 x sys_clock 4 x sys_clock 8 x sys_clock 16 x sys_clock k. Row Blanking Time 142 x TSYS_CLOCK 282 x TSYS_CLOCK 562 x TSYS_CLOCK 1122 x TSYS_CLOCK Nrof_lines Register Row Blanking Time [s] 3.55 7.05 14.05 28.05
If BLACK is set to 1, the internal black signal is held high continuously. As a result, the column amplifiers are disconnected from the buses, and the buses are set to the voltage given by DAC_DARK. The output of the amplifier equals the voltages from the offset DACs. i. Reset_all (Bit 11) If RESET_ALL is set to 1, all the pixels are simultaneously put in a 'reset' state. In this state, the pixels behave logarithmically with light intensity. If this state is combined with one of the NDR modes, the sensor can be used in a nonintegrating, logarithmic mode with high dynamic range. j. Nrof_pixels Register After the internal X_SYNC is generated (start of the pixel readout of a particular row), the PIXEL_VALID signal goes high. The PIXEL_VALID signal goes low when the pixel counter reaches the value loaded in the NROF_PIXEL register and an EOL pulse is generated. Due to the fact that two pixels are addressed at each internal clock cycle, the amount of pixels read out in one row is 2*(NROF_PIXEL + 1).
After the internal YL_SYNC is generated (start of the frame readout with Y_START), the line counter increases with each Y_CLOCK pulse until it reaches the value loaded in the NROF_LINES register and an EOF pulse is generated. In NDR Mode 2, the line counter increments only every two Y_CLOCK pulses and the EOF pulse shows up only after the readout of the row indicated by the right shift register INT_TIME Register When the Y_START pulse is applied (start of the frame readout), the sequencer generates the YL_SYNC pulse for the left Y-shift register. This loads the left Y-shift register with the pointer loaded in Y_REG register. At each Y_CLOCK pulse, the pointer shifts to the next row and the integration time counter increases (increment only every two Y_CLOCK pulses in NDR mode 2) until it reaches the value loaded in the INT_TIME register. At that moment, the YR_SYNC pulse for the right Y-shift register is generated, which loads the right Y-shift register with the pointer loaded in Y_REG register (shown in Figure 20 on page 21).
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Figure 20. Syncing of Y-shift Registers
Sync of left shift-register
Sync of right shift-register
Last line, followed by sync of left shift-register
Sync Line n Treg_int Tint
Treg_int: Difference between left and right pointer = integration counter until value "n" of INT_TIME register is reached = INT_TIME register In case of NDR = 0, the actual integration time Tint is given by TintL: Integration time [# lines] = NROF_LINES register - INT_TIME register + 1 In case of NDR = 1, NDR mode 1, the time Tint between two readings of the same row is given by: Tint:Integration time [# lines] = NROF_LINES register + 1
In case of NDR = 1, NDR mode 2, the times Tint1 and Tint2 between two readings of the same row (alternatingly) are given by: Tint1: Integration time [# lines] = 2 * INT_TIME register + 1 Tint2: Integration time [# lines] = 2 * (NROF_LINES register + 1) - (2 * INT_TIME register + 1) DELAY Register The DELAY register can be used to delay the PIXEL_VALID pulse (bits 0:3) and the EOL/EOF pulses (bits 4:7) to synchronize them to the real pixel values at the analog output or the ADC output (which give additional delays depending on their settings). The bit settings and corresponding delay are indicated in Table 13.
Table 13. Added Delay by Changing the DELAY Register Settings Bits 0000 0001 0010 0011 0100 0101 0110 0111 X_REG Register The X_REG register determines the start position of the window in the X-direction. In this direction, there are 2208 + 2 + 12 readable pixels. In the active pixel array, sub sampling blocks are 24 pixels wide and the columns are read two by two. Therefore, the number of start positions equals 2208/24 +2/2 +12/2 = 92 + 1 + 6 = 99. Y_REG Register The Y_REG register determines the start position of the window in the Y-direction. In this direction, there are 3000 + 2 + 12 readable pixels. In the active pixel array, sub sampling blocks are 24 pixels wide and the rows are read one by one. Therefore, the number of start positions equals 3000/24 + 2/2 +12 = 125 + 1 + 12 = 138. Delay [# SYS_CLOCK periods] 0 0 0 1 2 3 4 5 Bits 1000 1001 1010 1011 1100 1101 1110 1111 Image_core Register Bits 0:1 of the IMAGE_CORE register defines the several test modes of the image core. Setting 00 is the default and normal operation mode. If the bit is set to 1, the odd (bit 0) or even (bit 1) columns are tight to VDD. These test modes can be used to tune the sampling point of the ADCs to an optimal position. Bits 2:7 of the IMAGE_CORE register define the sub sampling mode in the X-direction (bits 2:4) and in the Y-direction (bits 5:7). The sub sampling modes and corresponding bit setting are given in the section Analog to Digital Converter on page 11. Delay [# SYS_CLOCK periods] 6 7 8 9 10 11 12 13
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AMPLIFIER Register a. Gain (Bits 0:3) The gain bits determine the gain setting of the output amplifier. They are effective only if UNITY = 0. The gains and corresponding bit setting are given in Table 4 on page 10. b. Unity (Bit 4) If UNITY = 1, the gain setting of GAIN is bypassed and the gain amplifier is put in unity feedback. c. One_out If ONE_OUT = 0, the two output amplifiers are active. If ONE_OUT = 1, the signals from the two buses are multiplexed to output OUT1. The gain amplifier and output driver of the second path are put in standby. d. Standby If STANDBY = 1, the complete output amplifier is put in standby. This reduces the power consumption significantly. e. Delay_clk_amp The clock that acts on the output amplifier can be delayed to compensate for any delay that is introduced in the path from shift register, column selection logic, column amplifier, and buses to the output amplifier. Setting '000' is used as a baseline. Table 14. Added Delay by Changing the DELAY_CLK_AMP Bit Settings Bits 000 001 010 011 Delay [ns] 1.7 2.9 4.3 6.1 Bits 100 2.9 110 111 Delay [ns] Inversion + 8.3 Inversion + 9.7 Inversion + 11.1 Inversion + 12.3
ADC Register a. Standby_1 and standby_2 If only one or none of the ADCs is used, the other or both ADCs can be put in standby by setting the bit to 1. This significantly reduces the power consumption. b. One If OUT1 and OUT2 are both used and connected to ADC_IN1 and ADC_IN2 respectively, ONE must be 0 to use both ADCs and to multiplex their output to ADC_D<9:0>. If ONE = 1, the multiplexing is disabled. c. Switch If the two ADCs are used (ONE = 0) and internal pixel clock (EXT_CLK = 0), the ADC output is delayed with one system clock cycle if SWITCH = 1. If the two ADCs are used (ONE = 0) and an external ADC clock (EXT_CLK = 1) is applied, the ADC output is delayed with half ADC clock cycle if SWITCH = 1. If only one ADC is used, the digital multiplexing is disabled by ONE = 1, but SWITCH selects which ADC output is on ADC_D<9:0> (SWITCH = 0: ADC_1, SWITCH = 1: ADC_2). d. Ext_clk If EXT_CLK = 0, the internal pixel clock (that drives the X-shift registers and output amplifier, that is, half the system clock) is used as input for the ADC clock. If EXT_CLK = 1, an external clock must be applied to pin ADC_CLK_EXT (pin 46). e. Tristate If TRISTATE = 1, the ADC_D<9:0> outputs are in tri-state mode. f. Delay_clk_adc The clock that finally acts on the ADCs can be delayed to compensate for any delay introduced in the path from the analog outputs to the input stage of the ADCs. The same settings apply for the delay that can be given to the clock acting on the output amplifier (see Table 14). The best setting also depends on the delay of the output amplifier clock and the load of the output amplifier. It must be used to optimize the sampling moment of the ADCs with respect to the analog pixel input signals. Setting '000' is used as a baseline. g. Gamma If GAMMA is set to 0, the ADC input to output conversion is linear, otherwise the conversion follows a 'gamma' law (more contrast in dark parts of the window, lower contrast in the bright parts). h. Bitinvert If BITINVERT = 0, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted.
Dac_raw_reg and Dac_fine_reg Register These registers determine the black reference level at the output of the output amplifier. Bit setting 11111111 for DAC_RAW_REG register gives the highest offset voltage; bit setting 00000000 for DAC_RAW_REG register gives the lowest offset voltage. Ideally, if the two output paths have no offset mismatch, the DAC_FINE_REG register must be set to 10000000. Deviation from this value can be used to compensate the internal mismatch (see the section Offset DACs on page 10). Dac_raw_dark Register This register determines the voltage level that is put on the internal buses during calibration of the output stage. This voltage level is also continuously put on the reset buses in case of nondestructive readout (as a reset level for the double sampling FPN correction).
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Serial to Parallel Interface To upload the sequencer registers, a dedicated serial to parallel interface (SPI) is implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. The address must be uploaded first (MSB first), then the data (also MSB first). The elementary unit cell is shown in Figure 21. Sixteen of these cells are connected in series, having a common SPI_CLK form the entire uploadable parameter block. Dout of one cell is connected to SPI_DATA of the next cell (maximum speed is 20 MHz). The uploaded settings on the address/data bus are loaded into the correct register of the sensor on the rising edge of signal REG_CLOCK and become effective immediately. Figure 21. SPI Interface
16 outputs to address/data bus
D REG_CLOCK C
Q
SPI_DATA SPI_CLK
To address/data bus SPI_DATA SPI_CLK D C Q Dout
REG_CLOCK
E ntire uploadable addres s block
SPI_CLK
Unity C ell
SPI_DATA REG_CLOCK
A3
A2
A1
D0
Internal register upload
Timing Diagrams
Sequencer Control Signals
There are 3 control signals that operate the image sensor:

These control signals must be generated by the external system with the following time constraints to SYS_CLOCK (rising edge = active edge):

SYS_CLOCK Y_CLOCK Y_START
TSETUP >7.5 ns THOLD > 7.5 ns
It is important that these signals are free of any glitches. Figure 22. Relative Timing of the Three Control Signals
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Basic Frame and Line Timing
The basic frame and line timing of the IBIS4-6600 sensor is shown in Figure 23. The pulse width of Y_CLOCK must be a minimum of one clock cycle and three clock cycles for Y_START. As long as Y_CLOCK is applied, the sequencer stays in a suspended state. T1 T2 Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel reset levels, and start the readout of one line. It depends on the granularity of the X-sequencer clock (see Table 12 on page 20). Pixels counted by pixel counter until the value of Nrof_pixels register is reached. Pixel_valid goes high when the internal X_sync signal is generated. In other words, when the readout of the pixels is started. Pixel_valid goes low when the pixel counter reaches the value loaded in the Nrof_pixels register. Eol goes high Sys_clock cycle after the falling edge of Pixel_valid. EOF goes high when the line counter reaches the value loaded in the NROF_LINES register and the line is read (PIXEL_VALID goes low). The time delay between successive Y_CLOCK pulses needs to be equal to avoid any horizontal illumination (integration) discrepancies in the image.
T3 T4
Both EOF and EOL can be tied to Y_START (EOF) and Y_CLOCK (EOL) if both signals are delayed with at least 2 SYS_CLOCK periods to let the sensor run automatically. Figure 23. Basic Frame and Line Timing
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Pixel Output Timing
Using Two Analog Outputs Figure 24. Pixel Output Timing using Two Analog Outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after four SYS_CLOCK cycles when the internal X_SYNC (equal to start of PIXEL_VALID output) appears (see Figure 24). The PIXEL_VALID and EOL/EOF pulses can be delayed by the user through the DELAY register. T1: Row blanking time (see Table 12 on page 20) T2: 4 SYS_CLOCK cycles.
Multiplexing to One Analog Output The pixel signal at the OUT1 output becomes valid after five SYS_CLOCK cycles when the internal X_SYNC (equal to start of PIXEL_VALID output) appears (see Figure 25). The PIXEL_VALID and EOL/EOF pulses can be delayed by the user through the DELAY register. T1: Row blanking time T2: 5 SYS_CLOCK cycles.
Figure 25. Pixel Output Timing Multiplexing to One Analog Output
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ADC Timing Two Analog Outputs Figure 26 shows the timing of the ADC using two analog outputs. Internally, the ADCs sample on the falling edge of the ADC_CLOCK (in case of internal clock, the clock is half the SYS_CLOCK). T1: Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total pipeline delay of four pixels. Figure 26. ADC Timing using Two Analog Outputs
One Analog Output Figure 27 shows the timing of the ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK. T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles. Figure 27. ADC Timing using One Analog Output
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Pin Information
The following table lists all the pins and their functions. There are a total of 68 pins. All pins with the same name can be connected together. Table 15. Pin List Pin 1 2 3 4 5 Pin Name CMD_COL_CTU CMD_COL CMD_COLAMP CMD_COLAMP_CTU RCAL_DAC_DARK Pin Type Input Input Input Input Input 0 1.08 0.66 0.37 1.27 at code 128 DAC_DARK reg 0 2.5 0 2.5 0 0.78 0.97 Expected Voltage [V] Pin Description Biasing of columns (ctu). Decouple with 100 nF to GNDA. Biasing of columns. Connect to VDDA with R = 10 k and decouple to GNDA with C = 100 nF. Biasing of column amplifiers. Connect to VDDA with R = 100 k and decouple to GNDA with C = 100 nF. Biasing of column amplifiers. Connect to VDDA with R = 10 M and decouple to GNDA with C = 100 nF. Biasing of DAC for dark reference. Can be used to set output range of DAC. Default: Decouple to GNDA with C = 100 nF Biasing of DAC for output dark level. Can be used to set output range of DAC. Default: Connect to GNDA VDD of analog part [2.5V] GND (&substrate) of analog part VDD of digital part [2.5V] GND (&substrate) of digital part Biasing of first stage output amplifiers. Connect to VDDAMP with R = 50 k and decouple to GNDAMP with C = 100 nF. Biasing of second stage output amplifiers. Connect to VDDAMP with R = 25 k and decouple to GNDAMP with C = 100 nF. Biasing of third stage output amplifiers. Connect to VDDAMP with R = 100 k and decouple to GNDAMP with C = 100 nF. Clock of digital parameter upload. Shifts on rising edge. Serial address and data input. 16-bit word. Address first. MSB first. VDD of analog output [2.5V] (Can be connected to VDDA) Biasing of first stage ADC. Connect to VDDA_ADC with R = 50 k and decouple to GNDA_ADC with C = 100 nF. Biasing of second stage ADC. Connect to VDDA_ADC with R = 50 k and decouple to GNDA_ADC. Biasing of input stage ADC. Connect to VDDA_ADC with R = 180 k and decouple to GNDA_ADC with C = 100 nF. GND (&substrate) of analog output
6 7 8 9 10 11 12
RCAL_DAC_OUT VDDA GNDA VDDD GNDD CMD_OUT_1 CMD_OUT_2
Input Power Power Power Power Input Input
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CMD_OUT_3 SPI_CLK SPI_DATA VDDAMP CMD_FS_ADC CMD_SS_ADC CMD_AMP_ADC GNDAMP OUT1 ADC_IN1 VDDAMP OUT2 ADC_IN2 VDDD GNDD GNDA
Input Input Input Power Input Input input Ground Output Input Power Output Input Power Power Power
0.67 2.5 0.73 0.73 0.59 0
Black level: 1 at code 190 Analog output 1 DAC_RAW register See OUT1. 2.5 Analog input ADC 1 VDD of analog output [2.5V] (Can be connected to VDDA)
Black level: 1 at code 190 Analog output 2 DAC_RAW register See OUT2. 2.5 0 0 Analog input ADC 2 VDD of digital part [2.5V] GND (&substrate) of digital part GND (&substrate) of analog part Page 27 of 35
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Table 15. Pin List (continued) Pin 29 30 31 32 33 34 35 36 37 38 39 VDDA REG_CLOCK SYS_CLOCK SYS_RESET Y_CLK Y_START GNDD_ADC VDDD_ADC GNDA_ADC VDDA_ADC VHIGH_ADC Pin Name Pin Type Power Input Input Input Input Input Power Power Power Power Input 0 2.5 0 2.5 1.5 Expected Voltage [V] 2.5 Pin Description VDD of analog part [2.5V] Register clock. Data on internal bus is copied to corresponding registers on rising edge. System clock defining the pixel rate (nominal 40 MHz, 50% 5% duty cycle) Global system reset (active high) Line clock Start frame readout GND (&substrate) of digital part ADC VDD of digital part [2.5V] ADC GND (&substrate) of analog part VDD of analog part [2.5V] ADC high reference voltage (for example, connect to VDDA_ADC with R = 560 and decouple to GNDA_ADC with C = 100 nF) ADC low reference voltage (for example, connect to GNDA_ADC with R = 220 and decouple to GNDA_ADC with C = 100 nF) GND (&substrate) of analog part VDD of analog part [2.5V] GND (&substrate) of digital part ADC VDD of digital part [2.5V] ADC Variable reset voltage (dual slope) External ADC clock Diagnostic end of line signal (produced by sequencer), can be used as Y_CLK Diagnostic end of frame signal (produced by sequencer), can be used as Y_START Diagnostic signal. High during pixel readout Temperature measurement. Output voltage varies linearly with temperature. ADC data output (MSB) VDD of pixel core [2.5V] Anti-blooming ground. Set to 1V for improved anti-blooming behavior ADC data output ADC data output ADC data output ADC data output ADC data output ADC data output Reset voltage [2.5V]. Highest voltage to the chip. 3.3V for extended dynamic range or 'hard reset'. ADC data output ADC data output ADC data output (LSB) Page 28 of 35
40
VLOW_ADC
Input
0.42
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
GNDA_ADC VDDA_ADC GNDD_ADC VDDD_ADC VDD_RESET_DS ADC_CLK_EXT EOL EOF PIX_VALID TEMP ADC_D<9> VDD_PIX GND_AB ADC_D<8> ADC_D<7> ADC_D<6> ADC_D<5> ADC_D<4> ADC_D<3> VDD_RESET ADC_D<2> ADC_D<1> ADC_D<0>
Power Power Power Power Power Input Output Output Output Output Output Power Power Output Output Output Output Output Output Power Output Output Output
0 2.5 0 2.5 2.5 (for no dual slope) 2.5 0 2.5 -
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Table 15. Pin List (continued) Pin 64 65 66 67 68 Pin Name BS_RESET BS_CLOCK BS_DIN BS_BUS CMD_DEC Pin Type Input Input Input Output Input 0.74 Expected Voltage [V] Pin Description Boundary scan (allows debugging of internal nodes): Reset. Tie to GND if not used. Boundary scan (allows debugging of internal nodes): Clock. Tie to GND if not used. Boundary scan (allows debugging of internal nodes): In. Tie to GND if not used. Boundary scan (allows debugging of internal nodes): Bus. Leave floating if not used. Biasing of X and Y decoder. Connect to VDDD with R = 50 k and decouple to GNDD with C = 100 nF.
Note on Power On Behavior At power on, the chip is in an undefined state. It is advised that the power on is accompanied by the assertion of the SYS_CLOCK and a SYS_RESET pulse that puts all internal registers in their default state (all bits are set to 0). The X-shift registers are in a defined state after the first X_SYNC, which occurs a few microseconds after the first Y_START and Y_CLOCK pulse. Before this X_SYNC, the chip may draw more current from the analog power supply VDDA. It is therefore favorable to have separate analog and digital supplies. The current spike (if there are any) may also be avoided by a slower ramp up of the analog power supply or by disconnecting the resistor on pin 3 (CMD_COLAMP) at startup.
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Package Information
Figure 28. 68 Pin LCC Packaging Outline (001-05458)
26 27
10 9 9
10
26 27
GLASS 1 68 1 68
43 44 60
61
61 60 44
43
PART NO. TABLE
001-05458 **
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Figure 29. 84 Pin JLCC Packaging Outline (001-05462)
74 75
54 53 53
54
74 75
GLASS
84 1 84 1
11 12 32
33
33 32 12
11
A
84 JLCC PACKAGING OU
VIEW A
001-05462 ** 001-054
Document Number: 001-02366 Rev. *E
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IBIS4-6600 CYII4SM6600AB
Glass Lid Specifications
Monochrome Sensor A D263 glass is used as protection glass lid on top of the IBIS4-6600 monochrome sensors. The refraction index of the D263 glass lid is 1.52. Figure 30 shows the transmission characteristics of the D263 glass. Figure 30. Transmittance Curve of the D263 Cover Glass Lid
100 90 80 70 60 50 40 30 20 10 0 400 500 600 700 800 900
Transmission [%]
Wavelength [nm]
Storage and Handling
Storage Conditions
Table 16. Storage Conditions Description Temperature Minimum -30 Maximum +85 Maximum C
Manual Soldering When a soldering iron is used, the following conditions must be observed:

Use a soldering iron with temperature control at the tip. The soldering iron tip temperature must not exceed 350C. The soldering period for each pin must be less than 5 seconds.
Handling and Soldering Conditions
Special care must be taken when soldering image sensors with color filter arrays (RGB color filters), onto a circuit board, because color filters are sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. The following recommendations ensure that sensor performance is not compromised during end-users assembly processes. Board Assembly Device placement onto boards must be done in accordance with strict ESD controls for Class 0, JESD22 Human Body Model, and Class A, JESD22 Machine Model devices. Assembly operators must always wear all designated and approved grounding equipment. Grounded wrist straps at ESD protected workstations are recommended, including the use of ionized blowers. All tools must be ESD protected.
Reflow Soldering Figure 31 on page 33 shows the maximum recommended thermal profile for a reflow soldering system. If the temperature/time profile exceeds these recommendations, damage to the image sensor may occur. See Figure 31 on page 33 for more details. Precautions and Cleaning Avoid spilling solder flux on the cover glass, because bare glass and particularly glass with antireflection filters may be adversely affected by the flux. Avoid mechanical or particulate damage to the cover glass. It is recommended that isopropyl alcohol (IPA) be used as a solvent for cleaning the image sensor glass lid. When using other solvents, it must be confirmed beforehand whether the solvent can dissolve the package and/or the glass lid.
Document Number: 001-02366 Rev. *E
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IBIS4-6600 CYII4SM6600AB
Figure 31. Reflow Soldering Temperature Profile
RoHS (Pb-Free) Compliance
This section reports the use of Hazardous chemical substances as required by the RoHS Directive (excluding packing material). Table 17. The Chemical Substances and Information about Any Intentional Content Chemical Substance Lead Cadmium Mercury Hexavalent chromium PBB (Polybrominated biphenyls) PBDE (Polybrominated diphenyl ethers) Pb-Free Soldering IBIS4-A-6600-M2 (serial numbers beyond 3694): This product is successfully tested for Pb-free soldering processes, using a reflow temperature profile with maximum 260C, minimum 40s at 255C, and minimum 90s at 217C. IBIS4-A-6600-C2: This product does not withstand a lead-free soldering process. Maximum allowed reflow or wave soldering temperature is 220C. Hand soldering is recommended for this part type. Note that "Intentional content" is defined as any material demanding special attention is contained into the inquired product by following cases: 1. A case that the previously mentioned material is added as a chemical composition into the inquired product intentionally, to produce and maintain the required performance and function of the intended product. 2. A case that the previously mentioned material, which is used intentionally in the manufacturing process, is contained in or adhered to the inquired product. Intentional Content NO NO NO NO NO NO Portion Containing Intentional Content The following case is not treated as "intentional content": A case that the previously mentioned material is contained as an impurity into raw materials or parts of the intended product. The impurity is defined as a substance that cannot be removed industrially, or is produced at a process, such as chemical composing or reaction and cannot be removed technically.
Document Number: 001-02366 Rev. *E
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IBIS4-6600 CYII4SM6600AB
Ordering Information
Table 18. Ordering Information Cypress Part number CYII4SC6600AB-QDC CYII4SM6600AB-QDC CYII4SC6600AB-HDC CYII4SM6600AB-HDC Package 68-pin LCC 68-pin LCC 84-pin JLCC 84-pin JLCC Glass Lid D263 D263 D263 D263 Mono/Color RGB Bayer pattern Black and White RGB Bayer pattern Black and White
* JLCC package for use in evaluation kits only. ** D263 is used as monochrome glass lid (see Figure 30 on page 32 for spectral transmittance). Other packaging combinations are available upon special request. Note The IBIS4-6600 sensor is to be used only in applications not related to Low Vision Aid Applications. A strict exclusivity agreement prevents Cypress from selling the IBIS4-6600 sensor to customers who intend to use it for the above specified applications.
Document Number: 001-02366 Rev. *E
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IBIS4-6600 CYII4SM6600AB
Document History Page
Document Title: IBIS4-6600 CYII4SM6600AB 6.6 MP CMOS Image Sensor Document Number: 001-02366 REV. ** *A *B *C *D *E ECN 384900 402976 418669 502551 642596 2649816 Submission Date See ECN See ECN See ECN See ECN See ECN 03/17/2009 Orig. of Change FWU FWU FVK QGS FPW Origination. Preliminary notice removed. Electro optical spec updated to characterization data. Table 15. ADC resistor values changed. ADC section added. Figure 33 p41 corrected Converted to Frame file Ordering information update Description of Change
PCI/AESA Final data sheet. Changed title from "IBIS4-A-6600 CMOS Image Sensor" to "IBIS4-6600 CYII4SM6600AB 6.6 MP CMOS Image Sensor". Updated Typical Response Curve of the RGB Filters on page 7 and added Relative Response Graph on page 8. Updated Package Diagrams and data sheet template.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. For more information on Image sensor products, please contact imagesensors@cypress.com. Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications. Consumer applications include the fast growing high volume cell phone, digital still cameras as well as automotive applications. Cypress' CMOS image sensors are characterized by very high pixel counts, large area, very high frame rates, large dynamic range, and high sensitivity.
(c) Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-02366 Rev. *E
Revised March 17, 2009
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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